Memtest86 full changelog

New Features
Added new configuration file parameter CHECKMEMSPEED for verifying whether the configured memory speed is consistent with one of the SPD profiles or an arbitrary minimum speed specified by the user. If this check fails, an error message is displayed and the memory test will not start. This is useful for confirming that the memory tests are carried out at the maximum speed supported by the RAM.
Added new configuration file parameter TCPREQUESTLOCATION for specifying the URL request path (and cloud API key) for PassMark Management Console integration
Added new configuration file parameter TCPGATEWAYIP for setting the default gateway route IP address to allow for connections outside the local network for PassMark Management Console integration
Added new configuration file parameter SPDREPORTEXTSN for specifying whether to use the module’s extended, 18-digit serial number or standard 8-digit JEDEC serial number in reports.

New Features:
Added support for CFGDEFAULT tag for multi-config files to specify the default configuration
Added support for CFGTIMEOUT tag for multi-config files to specify the timeout in seconds
Fixes/Enhancements:
Fixed possible divide by zero error when displaying file system info of attached disks
Fixed system address to UMC decoding for AMD Ryzen chipsets
Fixed incorrect transfer speed obtained for Alder Lake/Raptor Lake chipsets

New Features
Added 'SPDREPORTBYELO' and 'SPDREPORTBYTEHI' configuration parameter for specifying the SPD byte range to display in the HTML report
Implemented workaround for reading DDR5 SPD when SPD write disable (SPDWR) is set for Intel chipsets
Added DIMM/IC decoding support for AMD Phoenix (19h 74h) chipsets
Fixes/Enhancements
Added support for chipsets with up to 12 memory controllers
Fixed hang due to reading non-existent MSR registers for AMD 19h 60-6fh chipsets
Fixed channel decoding for AMD Ryzen Zen 2/4 chipsets
Fixed incorrect memory clock reported for Intel Alder Lake/Rocket Lake chipsets
Fixed incorrect memory clock reported for AMD 19h 60-6fh chipsets
Fixed incorrect CPU temperature reported for EPYC 7003 series chipsets due to temperature offsets
Fixed DIMM temperature read failure after reading SPD for certain DDR5 modules
Added reporting of additional DDR5 SPD attributes
Fixed hang due memory allocation issues for Intel Skylake/Kaby Lake chipsets